 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| xr OCTOBER 2005 XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS REV. 1.0.1 GENERAL DESCRIPTION The XRK32510 is a high performance, low jitter, low skew clock driver. The XRK32510 uses phase-lock loop (PLL) tecnology to synthesize the CLK_IN signal into 10 output signals (QA), synchronized in both phase and frequency. XRK32510 features low skew, low jitter and 50% duty cycle making it a perfect fit in dual in line memory module (DIMM) board clocking, PC133 SDRAM designs and other server applications. The 10 outputs can be disabled using the Output Enable (OE) pin. By connecting the Feedback Output (FB_OUT) signal to the Feedback Input (FB_IN) signal, the propagation delay from CLK_IN to the 10 buffered Outputs is nearly zero. FIGURE 1. BLOCK DIAGRAM OF THE XRK32510 FEATURES * Spread Spectrum Clock Compatible * Operating frequency range: 25MHz to 175MHz * Low noise * Low jitter internal PLL * No external RC filter components required * Meets or exceeds DPC133 registered DIMM specification 1.1 * Output Enable (OE) pin can be used to disable the CLCK_OUT pins * Operating supply of 3.3V VDD * Plastic 24 Pin TSSOP package FB_OUT QA0 QA1 QA2 QA3 CLK_IN Ref 0 QA4 PLL FB_IN 1 QA5 QA6 AVDD QA7 QA8 QA9 OE PRODUCT ORDERING INFORMATION PRODUCT NUMBER XRK32510CG PACKAGE TYPE 24 Pin TSSOP OPERATING TEMPERATURE RANGE 0C to +70C Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS FIGURE 2. PIN OUT OF THE XRK32510 xr REV. 1.0.1 AGND VDD QA0 QA1 QA2 GND GND QA3 QA4 VDD OE FB_OUT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLK_IN AVDD VDD QA9 QA8 GND GND QA7 QA6 QA5 VDD FB_IN 2 XRK32510 xr REV. 1.0.1 XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS PIN DESCRIPTIONS PIN # 1 2 10 14 11 PIN NAME AGND VDD VDD VDD OE TYPE **** **** Analog Ground 3.3V Power Supply PIN DESCRIPTION INPUT Output Enable: "High" = Normal operation, Clock outputs (QA[0:9]) enabled "Low" = Clock outputs (QA[0:9]) disabled Feedback Output: When this pin is connected to FB_IN, the propagation delay from CLK_IN to any of the 10 QA pins will be nearly zero. Feedback Input Buffered Clock Outputs: These 10 outputs provide low-skew, low jitter, 50% duty cycle renditions of CLK_IN 12 FB_OUT OUTPUT 13 3 4 5 8 9 15 16 17 20 21 22 23 FB_IN QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 QA9 VDD AVDD INPUT OUTPUT(S) **** **** 3.3V Digital Power Supply 3.3V Analog Supply: If this pin is connected to ground, the PLL is disabled and will be bypassed and the CLK_IN signal will be connected directly to the output buffers of the 10 QA pins. Reference Clock Input 24 CLK_IN INPUT FUNCTIONAL OPERATION INPUTS OE 0 1 AVDD 3.3V 3.3V QA[0:9] 0 Driven BUFFER MODE 0 1 0 0 0 Driven Driven Driven CLK_IN CLK_IN OFF OFF OUTPUTS FB_OUT Driven Driven SOURCE PLL PLL PLL CONDITION ON ON 3 XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS xr REV. 1.0.1 ABSOLUTE MAXIMUM RATINGS Analog Supply Voltage (AVDD) Supply Voltage (VDD) Logic Inputs Ambient Operating Temperature Range Storage Temperature Range AVDD < (VDD +0.7V) 4.3V GND- 0.5V to VDD + 0.5V 0C to +70C -65C to +150C ELECTRICAL CHARACTERISTICS -OUTPUT TA = 0 - 70C, VDD = AVDD = 3.3V +/- 10%, CL = 20 - 30pF, RL = 470, (unless otherwise stated) SYMBOL RDSP RDSN VOH VOL PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage 2.4 MIN TYP 36 32 3.0 0.2 -33 IOH Output High Current 19 IOL Tr Tf Dt Output Low Current Rise Time1 Fall Time1 Duty Cycle1 13 0.5 0.5 45 -48 28 19 0.8 0.9 50 28.7 Tcyc-cyc TjABS Tsk Tpe Tpej DR1 Cycle to Cycle Jitter1 25 57 29 -150 -50 35 3.5 150 150 50 3.7 2.1 2.7 55 100 75 ps ps ps ps ps ns mA ns ns % -13.6 -22 mA MAX UNITS V CONDITIONS VO = VDD/2 VO = VDD/2 IOH = -8mA IOL = 8mA VOH = 2.4V VOH = 2.0V VOL = 0.8V VOL =0.55V VOH = 2.0V, VOL = 0.8V VOL = 0.8V, VOH = 2.0V VT = 1.5V, CL = 30pF @66 - 100MHz, loaded outputs @133MHz, loaded outputs 10,000 cycles, CL = 30 pF VT = 1.5V (Window) Output to Output VT = VDD/2, CLK_IN to FB_IN VT = VDD/2, CLK_IN to FB_IN, Delay Jitter VT = 1.5V, PLL Disabled (AVDD = 0) Absolute Jitter1 Skew1 Phase Error1 Phase Error Jitter1 Delay Input to Output1 NOTE: 1. Guaranteed by design, not 100% tested in production 4 xr REV. 1.0.1 XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS ELECTRICAL CHARACTERISTICS - INPUT AND SUPPLY TA = 0 - 70C, VDD= AVDD = 3.3V +/- 10% (unless otherwise stated) SYMBOL VIH VIL IIH IIL IDD CIN CO PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Operating Current Input Capacitance Output Capacitance MIN 2 GND 0.3 0.1 19 140 4 8 TYP MAX VDD + 0.3 0.8 100 50 170 UNITS V V A A mA pF pF VIN = VDD VIN = 0V CL = 0pF, FIN = 66MHz Logic Inputs Logic Outputs CONDITIONS 5 XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS FIGURE 3. PACKAGE OUTLINE DRAWING xr REV. 1.0.1 6 xr REV. 1.0.1 XRK32510 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS REVISIONS REV. # 1.0.0 1.0.1 DATE 9/23/05 10/06/05 Initial issue. DESCRIPTION OF CHANGES Product ordering information: Remove "F" product numbers and Lead Free column. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2005 EXAR Corporation Datasheet October 2005. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 7 |
Price & Availability of XRK32510CG
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |